The present invention relates to the manufacture of objects. More particularly, the invention provides a method and resulting structure for a memory device using a ferroelectric material.
Memory cells are used in the implementation of many types of electronic devices and integrated circuits. These devices include microprocessors, static random access memories (“SRAMs”), erasable-programmable read only memories (“EPROMs”), electrically erasable programmable read only memories (“EEPROMs”), Flash EEPROM memories, programmable logic devices (“PLDs”), field programmable gate arrays (“FPGAs”), application specific integrated circuits (“ASICs”), among others. Memory cells are used to store the data and other information for these and other integrated circuits.
As integrated circuit technology and semiconductor processing continue to advance, there is a need for greater densities and functionality in integrated circuits, which are often determined in a large part by the size of the memory cells. Further, it is desirable that the memory cells have improved operating characteristics, such as lower power consumption, nonvolatility, greater device longevity, improved data retention, better transient performance, superior voltage and current attributes, and improvements in other similar attributes.
Volatile memory devices are commonly used in many integrated circuit applications. These memory devices include, among others, dynamic random access memory (“DRAMs”) and others. Unfortunately, DRAM devices often require power to maintain the memory state of the device. Accordingly, other devices such as flash memory devices and the like have been proposed. These devices, however, are often larger and more difficult to scale than DRAM devices.
Other types of technologies such as ferroelectric random access memory (“FRAM”) devices have also been proposed. FRAM devices attempt to take advantage of the densities of the DRAM designs to create a non-volatile memory cell. Here, the ferroelectric material is often used as an alternative-material to replace conventional capacitor materials of DRAMs with the FRAM capacitor. An example of this technology has been proposed by Ramtron International of Colorado in the United States. A variety of limitations also exist with this FRAM technology. For example, a one transistor and one capacitor approach uses a reading process that is often destructive to support the charges. This is commonly called destructive read out process, also called DRO. After each read, the state must often be reinstated, which often calls for an additional programming step. Continued read and write operations degrade the FRAM material, and causes reduced reliability and efficiency of the device.
Furthermore, the FRAM capacitor size is often fixed in size. This size cannot be changed, according to scaling rules. Here, the transistor size is reduced but capacitance cannot be reduced. FRAM capacitors therefore cannot be reduced according to manufacturing problems. FRAM capacitors are often plagued with contamination and also process compatibility and reliability. Accordingly, conventional FRAM devices are often difficult to make for highly dense devices.
What is needed is an improvement FRAM technique for the manufacture of memory devices.